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Re: PIC A/D conversion jitter

From: Norm White   normillscsinternet.com
Date: Mon, 24 Apr 2006 11:06:03 -0700

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Hi Sandor

You might try a software solution to your ADC jitter problem:
Create a n-stage FIFO shift register. After shifting each new
reading into the FIFO, average all the data in the FIFO and
use that average instead of the raw reading. "n" doesn't have
to be very long... 8 stages should deal with most asymmetric
1-bit jitter. Go to more stages if the jitter persists. But
don't use more stages than you have to, as that will make the
response unduly sluggish.

Another thing you could try is estimate what is the smallest
data change that is usually associated with someone actually
messing with the knob, and ignore any change that is less.
This assumes you are getting only data jitter, and not drift.


Norm
--



Sandor Ajzenstat wrote: 
Dear ARG list,



I have a question regarding the PIC18F452 and A/D jitter. Any suggestions you can make would be greatly appreciated.



I am using a 1K 2Watt carbon potentiometer. The pot has terminals 1 & 3 (terminals at either end of the resistive element) connected to +5V and Ground, which are common to the PIC's VDD and VSS. The potentiometer wiper terminal is wired to the PIC analog input AN0.



I am finding that if I make a number of readings with no changes to the potentiometer I get variations in the digital value determined by the A/D. Depending on the pot setting this can affect the lowest 4 bits of conversion, for example: for a specific pot setting I get a fluctuation between 0x77 and 0x78.



Issues of offset error and calibration are not a problem for me, but my application requires a consistent unchanging digital conversion for a specific potentiometer setting. I only need 8 significant bits, so I can loose the two lsb bits from the 10 bit conversion, but even so I find I get variations in digital conversion when the pot is not adjusted.



The problem seems to become worse when I touch the potentiometer. It has been explained to me this suggests the pot might be acting as an antenna. I have tried grounding the pot chassis, but this has not helped.



I have checked all the eratta sheets for this PIC.



Things I have tried which have not affected this issue:



(1) use of VREF+ and VREF- instead of VSS and VDD for the reference voltage

(2)        grounding the potentiometer chassis

(3)        various kinds of pi filter on the pot wiper terminal output

(4)        10 uF cap across pot terminals 1 and 3



Things I have not yet tried:



(1)        Replace pot with one that has a cermet resistive element

(2) Replace PIC with 18F4520



Again, thank you for any help or ideas you may have. I appreciate your time in this regard.



Sincerely,

Sandor Ajzenstat



p.s. Specific note to Bob B: I've considered your suggestion, but I'm not sure how it will help. I guess I didn't make it clear at the time that the pot terminals 1 & 3 are at +5 and GND. Take care, S.









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